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Linux Foundation and RISC-V International launch free courses on open source architecture for processors

The online courses are seven weeks long and offer free and paid options.

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The Linux Foundation and RISC-V International hope that two new free courses will make it easier for IT professionals to learn about open instruction set architecture for processor chips. The courses are available starting Tuesday, March 2 on 

An ongoing semiconductor chip shortage due to supply chain interruptions has limited the supply of smartphones and laptops, but the ripple effects extend beyond the tech market, as Dallon Adams reported on TechRepublic. Ford recently announced that it was decreasing F-150 production due to the semiconductor shortage.

RISC-V (pronounced as “risk five”) is an open instruction set architecture that could power a new era of innovation for processor architectures. According to a press release, The Linux Foundation and RISC-V International designed these courses to reduce the barrier to entry for people interested in gaining RISC-V skills. RISC-V International is a non-profit based in Switzerland with more than 750 members. 

SEE: RISC-V: What it is, and what benefits it can provide to your organization 

“RISC-V International is committed to providing opportunities for people to gain a deeper understanding of the RISC-V ISA and expand their skills,” Calista Redmond, CEO of RISC-V International, said in a press release. “These courses will allow everyone to build deeper technical insight, learn more about the benefits of open collaboration, and engage with RISC-V for design freedom.”

The two classes are:

  1. Introduction to RISC-V: This course explains the basics of the RISC-V ecosystem, including how to curate and develop RISC-V specifications and the technical aspects of working with RISC-V both as a developer and end user. The course provides the foundational knowledge needed to effectively engage in the RISC-V community, contribute to the ISA specifications, and develop a wide range of RISC-V software and hardware projects. The course was developed by Jeffrey Osier-Mixon, program manager for RISC-V International, and Stephano Cetola, technical program manager for RISC-V International. 
  2. Building a RISC-V CPU Core: This class focuses on digital logic design and basic central processing unit (CPU) microarchitecture. Participants will use the Makerchip online integrated development environment to build technologies ranging from logic gates to a simple and complete RISC-V CPU core. The class will cover a variety of emerging technologies supporting an open source hardware ecosystem, including RISC-V, transaction-level verilog, and the online Makerchip IDE. The class was developed by Steve Hoover, founder of Redwood EDA.

Both introductory courses are seven weeks long and require one to two hours per week of course work. Students can audit the courses for free through edX or pay $149 for each course to receive a verified certificate of completion. The paid version includes access to the course for a year as well as additional assessments and educational content.

SEE: Alibaba releases its first RISC-V CPU as open source solution for 5G and AI (TechRepublic)

An open source ISA means that anyone can use the specification to build an implementation for free. The ISA defines the interface between hardware and software and makes it easy to move software from different implementations of a particular ISA core.

As Scott Matteson explained, RISC-V is the fifth generation of the “reduced instruction set computer” style of chip architecture. Using an open source approach to making chips could reduce the cost for manufacturers.

RISC-V International sees this open architecture as a tool for building the next generation of chips.

Also see

This post was written by and was first posted to TechRepublic

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